The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having an air spacer between a gate and a contact. The present invention also relates to fabrication methods and resulting structures for a semiconductor device having an air gap between metal interconnect layers.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. Some non-planar transistor device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and performance over lateral devices. In contemporary VFET devices, in contrast to conventional FETs, the source to drain current flows through a vertical pillar in a direction that is perpendicular with respect to a horizontal major surface of the wafer or substrate. A VFET can achieve a smaller device footprint because its channel length is decoupled from the contacted gate pitch. Unfortunately, as device dimensions and component spacing shrink, parasitic capacitance tends to increase. Parasitic capacitance, or conductor-to-conductor capacitance, between two conductors is a function of the length and thickness of the conductors, as well as the distance separating the conductors.